1. Technical Field of the Invention
The present invention relates to the field of manufacturing of products, such as wafers containing semiconductor devices, and more particularly, to the improvement of manufacturing processes for these products. By comparing response variables with a process sequence of products, the sources of variation due to the order of processing of products through the process steps in the manufacturing process are determined.
2. Description of Related Art
The manufacture of most products, such as wafers containing semiconductor devices, requires a number of discrete processing steps to create the product. For the example of wafers, a number of discrete steps are needed to produce a packaged semiconductor circuit device from raw semiconductor material. The starting substrate is usually a slice of single crystal silicon referred to as a wafer. Circuits of a particular type are fabricated together in batches of wafers called "lots" or "runs". The fabrication process creates regular arrays of a circuit on the wafers of a lot. During processing, the individual wafers in a lot may go through individual processing steps one at a time or as a batch. At the completion of wafer processing the wafers are tested to determine circuit functionality. Later the wafers are sliced, the functioning products are packaged, and further testing occurs prior to use by the customer.
Data gathered during the course of wafer processing is used to diagnose yield problems and forms the basis of yield improvement efforts. Such data includes parametric electrical test data gathered on individual circuits and test structures fabricated on the wafers, as well as test data referred to as wafer sort data which tests the suitability for use once wafer processing is completed.
One of the possible sources of yield variation is the order at which wafers in a lot are processed at a given processing step. When the processing is done one wafer at a time at a step, a variation in yield may be due to build up of contaminants, heating of a processing chamber, or another physical effect which changes during the processing of the lot. In a batch operation, the physical location of the wafer in the batch processing equipment may influence uniformity of the processing effects across the lot. The benefits of tracking the order of wafer processing at critical processing steps and correlating this processing order to device performance (i.e., examining a linear correlation coefficient) in order to improve yields are well known. See, for example, "Wafer Tracking Comes of Age", Gary Scher, Semiconductor International (May 1991, pp. 126-131).
As an example, consider a critical lithography step in which the wafers in a lot are processed one at a time through a lithography system called a stepper. Assume that there is a contamination problem which causes contamination to build up on the chuck holding the wafer in place during exposure which worsens with each wafer processed. Normal practice may require the chuck to be cleaned prior to each lot being started. The contamination buildup causes the upper wafer surface to deviate from the ideal focal plane during exposure and irregular features are produced upon exposure. If the order in which each wafer is processed is known, then the final wafer yield may be plotted against the processing order in this step. In this example, for each wafer in the lot a drop-off in yield with processing order would be observed due to the contamination problem. Armed with this knowledge, process engineers responsible for this step could then begin work on fixing the problem and hence improving yield and profitability.
The tracking of the wafer processing order in the prior art used specialized equipment to read scribed wafer identifiers either immediately prior to or after critical processing steps and to store this data for later correlation with device performance. Randomizing the order of the wafers prior to such steps is often done to ensure effects are not confounded. The wafer positional data is fed into a computer system, the device performance metrics for a wafer lot of interest are manually entered, and then all possible graphs of the device metrics for that lot versus wafer processing order at each step are generated. An analyst reviews the graphs and examines linear correlation coefficients to determine those steps at which the processing order may affect performance by manually discerning trends in the graph plots.
Keeping track of the wafer-processing sequence within a run provides an efficient method of identifying the sources of systematic, wafer-positional effects on die yield and device parameters. However, most processes comprise many steps. Although the randomization of the wafer order at each step prevents any positional trend in one sector being carried over into the next sector, thereby isolating the sector responsible for the trend, there are high costs associated with this method. First, the machines needed to perform the randomization at each step requires an interface with the database to record the randomized sequences. The hardware or software to implement each interface is very costly. In a large fab, where there are many process steps, a large number of machines are needed for randomizing and interfacing with the database, making the financial costs extremely high.
A second problem associated with the above-described method is the amount of data generated in this system is exceptionally large. This data includes the order of the wafers at each processing point, for each lot of wafers. Hence, each lot of wafers is randomized differently at each processing step for the different lots of wafers. This information must then be stored for each lot of wafers. The disk space needed to store this amount of data greatly increases the overall cost of the system, and the increased number of software interfaces also reduces the reliability of the system.